The present invention relates to a memory system, and more particularly, to a memory system and a method for ensuring stability of data during a read operation.
Synchronous dynamic random access memory (SDRAM) operates in synchronization with a clock signal typically provided by a central processing unit (CPU). By synchronously operating in relation to a clock signal known to the CPU, a memory system incorporating the SDRAM may be accessed at high speed without wait time.
SDRAM is classified into single data rate SDRAM (SDR SDRAM) and double data rate SDRAM (DDR SDRAM). DDR SDRAM has a data transmission band that is twice broader than SDR SDRAM. For example, SDR SDRAM operates at 133 MHz and DDR SDRAM operates at 266 MHz.
Generally, SDR SDRAM and DDR SDRAM receive a read command and then output data after a predetermined output delay during a read operation. The output delay generally includes a valid output delay tSAC. The valid output delay tSAC determined generated by such factors such as pressure, volume, and temperature (PVT) and operating frequency. It may be shorter or longer than one clock period of the clock signal provided by the CPU.
DDR SDRAM typically includes a delay locked loop (DLL) circuit that is operated such that the valid output delay tSAC remains less than one clock period. However, the DLL circuit has relatively high power consumption. Mobile devices such as mobile phones and PDAs usually strive for reduced power consumption. Accordingly, the DDR SDRAM commonly used in mobile devices does not include a DLL circuit. Unfortunately, DDR SDRAM without the DLL circuit may not synchronize the valid output delay tSAC within one clock period. Thus, the valid output delay tSAC may become longer than the one clock period due to PVT, particularly where high frequency operation is desired.
FIGS. (FIGS.) 1 through 3 are read timing diagrams for a conventional DDR SDRAM operated within a typical memory system including a DDR SDRAM controller. The DDR SRAM controller reads data stored in the DDR SRAM during a defined read operation.
Referring to FIGS. 1 through 3, a DDR SRAM (“the memory”) receives a read command RD from the DDR SRAM controller (“the memory controller”) during the read operation. In response, the memory generates a data strobe signal DQS using a constituent strobe signal generator following a predetermined output delay. The output delay includes valid output delay tSAC and is expressed in terms of a column address strobe delay signal (CAS latency or “CL”), or one clock period (1clk)+tSAC. A system designer or end user may set the CL to be 2 clock periods or 3 clock periods, as desired. In the examples shown in FIGS. 1 through 3, the CL is assumed to be 2 clock periods.
During periods when the memory does not output data, the strobe signal generator maintains a floating state to reduce power consumption. However, when the memory performs a read operation, the strobe signal generator provides a data strobe signal having a rising edge following a pre-amble period. The strobe signal generator returns to a floating state following a post-amble period after the falling edge of the data strobe signal. Because contemporary memory device use a high frequency clock signal, the amplitude of the data strobe signal may become unstable due to an internal capacitance effect arising from the interaction of memory device components. Amplitude instability may cause temporal shifting in the rising and/or falling edges of the data strobe signal. Accordingly, conventional strobe signal generators increase the amplitude of the data strobe signal during the pre-amble and post-amble periods, in order to maintain proper temporal alignment of the rising and falling edges. In this manner, the conventional strobe signal generator seeks to ensure stability of the data strobe signal.
The memory is synchronized with the rising and falling edges of the data strobe signal DQS to output data to the memory controller. Additionally, the memory outputs the data strobe signal DQS to the memory controller.
The memory controller provides a predetermined delay to the data strobe signal DQS through a constituent delay circuit to smoothly perform sampling of the input data. The delay circuit typically shifts the data strobe signal provided by the memory by about 90°, but other delay values are possible.
The memory controller is synchronized with the 90°-shifted data strobe signal DQSin to sample data from the memory. The memory controller synchronously outputs sampled data DQin to an external circuit (e.g., a requesting device, such as a Central Processing Unit (CPU), a Digital Signal Processor (DSP), a hardware (H/W) engine, and I/O device, etc.) in relation to the rising edges r.e1 and r.e2 of the first two clock signal periods following a point determined by CL+1 (or CL+2, or CL+3). The sampled and synchronized output data DQin may thus be provided to the requested device. So, in the context of the foregoing approach, a user predefined clock signal period (e.g., CL+1, CL+2, and CL+3) determines when read data is provided to the memory controller.
FIG. 1 is a read operation timing diagram assuming a valid output delay tSAC of one clock period. In this case, the memory controller outputs the sampled data DQin synchronously with the rising edges r.e1 and r.e2 of the first two clock periods (clock signal CK) following the expiration of the clock signal period CL+1. The illustrated example shown in FIG. 1 assumes a valid output delay tSAC shorter than the one clock period 1clk. Therefore, the memory controller may output the sampled data DQin synchronously with the rising edges r.e1 and r.e2 of the first two clock periods CK following the expiration of the clock signal period CL+1.
FIG. 2 is a similar read operation timing diagram, except the valid output delay tSAC is now longer than one clock period, but shorter than two clock periods. In this case, the memory controller outputs the sampled data DQin synchronously with the rising edges r.e1 and r.e2 of the first two clock signals CK following expiration of the clock signal period CL+2.
FIG. 3 is yet another similar timing diagram for a read operation, except the valid output delay tSAC is longer than two clock periods but shorter than three clock periods. In this case, the memory controller outputs the sampled data DQin synchronously with the rising edges r.e1 and r.e2 of the first two clock signals CK following expiration of the clock signal period CL+3.
In a case where the output point of the sampled data DQin by the memory controller is defined in relation to a clock signal period of CL+1 (re. FIG. 1), the memory controller will properly output the sampled data DQin so long as the valid output delay tSAC is less than or equal to one clock period. However, as illustrated in FIGS. 2 and 3, if a maximum valid output delay tSAC is expected to be greater than one clock period, the synchronous output point for the sampled data DQin must be defined in relation to a longer clock signal period (e.g., CL+2 or CL+3). Where an established output point for the memory controller varies from the actual data performance, the memory controller may not properly output the sampled data DQin, or may output only a portion of the sampled data DQin. This outcome is true whether the output point is defined in relation a clock signal period CL+2, or a clock signal period of CL+3, where the valid output delay tSAC is greater than the period allowed by the clock signal period.
To resolve the above limitations, a user typically sets the output point for the sampled data DQin in the memory controller with the largest available clock signal period (i.e., CL+3 in the working example) in order to establish a data output point for the memory controller with greatest reliability. However, this precaution merely ensures that a requesting device receives its read data at the latest possible point in time relative to the operation of the memory and memory controller.
Were the memory to include a DLL circuit, as is the common case of personal computers, the valid output delay tSAC would always be less than or equal to one clock period. Hence, the operation of the memory and memory controller would be consistent with the example illustrated in FIG. 1, (i.e., the rising edge R.e of the data strobe signal would be set with the rising edge r.e of the clock signal CL, and the data output point for the memory controller would be defined in relation to a clock signal period CL+1).
However, this same can not be said for most memory devices incorporated in mobile devices. Here, because of the absence of a DLL, the valid output delay can not be ensured at less than or equal to one clock period. Accordingly, the rising edge R.e of the data strobe signal may be later than the rising edge r.e of the clock signal CK. The delay of the data strobe signal becomes relatively longer as the period of the clock signal CK becomes shorter at higher operating frequencies. Thus, as the period of the clock signal CK becomes shorter and the delay of the strobe signal becomes longer, the valid output delay tSAC becomes longer than one clock period (1 clk) and results illustrated in FIGS. 2 and 3 arise.